The present invention relates to a prefetch queue for use in a memory controller chipset.
As is known, modern computer systems may include a memory controller that controls access of other agents, such as microprocessors or peripheral components, to system memory. The memory controller may communicate with the other agents via one or more communication buses. Different bus protocols may be used for the different buses.
A memory controller is a transaction processing system that typically interfaces to a memory array. The memory array includes a plurality of memory entries that store data. The transaction controller receives requests for data operations that are posted on one or more communication buses, determines which can be satisfied from the memory array and performs the data requests. Data requests include requests from an agent for data to be read from or written to the memory array.
Memory arrays are bandwidth limited. The bandwidth limitation constrains the rate at which data may be read from the array to an agent in response to a transaction request. The memory array introduces undesirable latency to such requests. Accordingly, there is a need in the art for a memory control system that reduces latency of read requests posted to memory arrays.
An embodiment of the present invention provides a memory controller that includes an arbiter, a prefetch cache in communication with the arbiter, and a prefetch queue in communication with the prefetch cache.